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Understanding the NXP i.MX6UL Pin Mux (Part 2)

In the previous post, it was noted that bit 30 needs to be set in the i.MX6UL pad config if you want to read the state of a GPIO output. Digging into this a bit more, we find the following text in the Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt file:

SION(1 << 30): Software Input On Field.
Force the selected mux mode input path no matter of MUX_MODE functionality. By default the input path is determined by functionality of the selected mux mode (regular).

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Understanding the NXP i.MX6UL Pin Mux

(note, the article is also applicable to the i.MX6ULL as these processors are very similar)

The NXP i.MX6UL application processor has a very flexible pin multiplexer, that is somewhat difficult to understand at first glance.  Most times when we’re configuring the pin mux in Linux, we modify Device Tree files, so perhaps that is the place to start.  The pin mux options for the i.MX6UL are defined in the arch/arm/boot/dts/imx6ul-pinfunc.h file.  The arguments to the macros in this file are defined as:

/*
 * The pin function ID is a tuple of
 * <mux_reg conf_reg input_reg mux_mode input_val>
 */
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Memory Performance on various Embedded Systems

Marcin just published an interesting article about memory performance on various embedded systems using the hdparm -T as a simple benchmarq.  This test gives a pretty good indicator of memory performance in the system.  From the hdparm man page:

Perform timings of cache reads for benchmark and comparison purposes.  For meaningful results, this operation should be repeated 2-3  times on an otherwise inactive system (no other active processes) with at least a couple of megabytes of free memory.  This displays the speed of reading directly from the Linux buffer cache without disk access.  This measurement is essentially an indication of the throughput  of  the processor, cache, and memory of the system under test.

A few results I find interesting:

  • modern desktop systems have an order of magnitude more memory bandwidth than ARM systems.
  • the i.MX31 is the highest performing ARM device tested
  • the i.MX31 performs better than the OMAP3 in this test — why is this?  As the ratio is 2, I’m guessing the bus is twice as wide?